Texas (TX)'s Hardware Sensing Δ 5th of January 2014 Ω 1:46 PM

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~ Texas Instruments ~ TI Multicore DSP TMS320C6474 ~ Technical Briefs from TI	~ DSP News ~ sense for Ξ ~ sense for Ξ	~ sense for Ξ ~ sense for Ξ ~ sense for Ξ
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«U.S. Hardware Sensing	Θ	Θ
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~ Texas Instruments

Texas Instruments

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~ TI Multicore DSP TMS320C6474

TI Multicore DSP TMS320C6474
CPU 3 C64x+
Peak MMACS 24000 (16-bit)
Frequency(MHz) 1000
On-Chip L1/SRAM 192 KB (3 x 64 KB per core)
On-Chip L2/SRAM 3072 KB
AIF/FSM 1 (six lanes)
EMIF 1 32-Bit DDR2 EMIF
External Memory Type Supported DDR2 SDRAM
DMA 64-Ch EDMA
ETB Yes
Serial RapidIO 1 (two lanes)
EMAC 10/100/1000
McBSP 2
I2C 1
Trace Enabled Yes
Timers 6 64-Bit GP
Hardware Accelerators VCP2,TCP2
Core Supply (Volts) 0.9 V to 1.2 V SmartReflex
IO Supply (Volts) 1.8 V, 1.1 V
Operating Temperature Range (°C) 0 to 100 (case)

Features

* High-Performance Multicore DSP (C6474)
o 1-ns Instruction Cycle Time
o 1.0-GHz Clock Rate
o Eight 32-Bit Instructions/Cycle
o Commercial Temperature 0°C to 100°C
* 3 TMS320C64x+™ DSP Cores
o Dedicated SPLOOP Instructions
o Compact Instructions (16-Bit)
o Exception Handling
* TMS320C64x+ Megamodule L1/L2 Memory Architecture
o 256 K-Bit (32 K-Byte) L1P Program Cache [Direct Mapped]
o 256 K-Bit (32 K-Byte) L1D Data Cache [2-Way Set-Associative]
o 24 M-Bit (3072 K-Byte) Total L2 Unified Mapped RAM/Cache [Flexible Allocation]
+ Configurable at boot-time to 1 MB/1 MB/1 MB or 1.5 MB/1 MB/0.5 MB
o 512 K-Bit (64 K-Byte) L3 ROM
* Enhanced VCP2
o Supports Over 694 7.95-Kbps AMR
* Enhanced Turbo Decoder Coprocessor (TCP2)
o Supports up to Eight 2-Mbps 3 GPP (6 Iterations)
* Endianness: Little Endian, Big Endian
* Frame Synchronization Interface
o Time Alignment Between Internal Subsystems, External Devices/System
o OBSAI RP1 Compliant for Frame Burst Data
o Alternate Interfaces for non-RP1 and non-UMTS Systems
* 16-/32-Bit DDR2-667 Memory Controller
* EDMA3 Controller (64 Independent Channels)
* Antenna Interface
o 6 Configurable Links (Full Duplex)
o Supports OBSAI RP3 Protocol, v1.0
o 768-Mbps, 1.536-, 3.072-Gbps Link Rates
o Supports CPRI Protocol V2.0
o 614.4-Mbps, 1.2288-, 2.4576-Gbps Link Rates
o Clock Input Independent or Shared with CPU (Selectable at Boot-Time)
* Two 1x Serial RapidIO® Links, v1.2 Compliant
o 1.25-, 2.5-, 3.125-Gbps Link Rates
o Message Passing and DirectIO Support
o Error Management Extensions and Congestion Control
* One 1.8-V Inter-Integrated Circuit (I2C) Bus
* Two 1.8-V McBSPs
* 1000 Mbps Ethernet MAC (EMAC)
o IEEE 802.3 Compliant
o Supports SGMII, v1.8 Compliant
o 8 Independent Transmit (TX) and 8 Independent Receive (RX) Channels
* Six 64-Bit General-Purpose Timers
o Configurable up to Twelve 32-Bit Timers
o Configurable in a Watchdog Timer mode
* 16 General-Purpose I/O (GPIO) Pins
* Internal Semaphore Module
o Software Method to Control Access to Shared Resources
o 32 General Purpose Semaphore Resources
* System PLL and PLL Controller
* DDR PLL and PLL Controller, Dedicated to DDR2 Memory Controller
* Supports IP Security
* IEEE-1149.1 and IEEE-1149.6 (JTAG™) Boundary-Scan-Compatible
* 561-Pin Ball Grid Array (BGA) Packages (CUN, GUN, or ZUN Suffix), 0.8-mm Ball Pitch
* 0.065-mm/7-Level Cu Metal Process (CMOS)
* SmartReflex™ Class 0 Enabled - 0.9-V to 1.2-V Adaptive Core Voltage
* 1.8-V, 1.1-V I/Os

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~ Technical Briefs from TI

TMS320C6474 Technical Briefs from TI

1 Key Message
ξ The TMS320C6474 DSP integrates three 1-GHz C64x+ DSP CPU cores,
ξ a host of high-speed peripherals, and
ξ large amounts of internal memory
ξ in a compact 23 mm by 23 mm package.
ξ These features allow the C6474 device to
ξ provide significant performance integration and high-performance density,
ξ along with substantial efficiencies in power, cost, and board space.

1.1 Key Features

High-Performance Multicore DSP (C6474)
ξ High-Performance Multicore DSP (C6474)
ξ 1-ns Instruction Cycle Time [2-Way Set-Associative]
ξ 1.0-GHz Clock Rate
ξ Commercial Temperature 0°C to 100°C

3 TMS320C64x+™ DSP Cores
ξ Dedicated SPLOOP Instructions
ξ Compact Instructions (16-Bit)
ξ Exception Handling

TMS320C64x+ Megamodule L1/L2 Memory Architecture
ξ 256 K-Bit (32 K-Byte) L1P Program Cache [Direct Mapped]

SDK
· Code Composer Studio™ 3.3
· DSP/BIOS™ 5.3
· DSP/BIOS™ 5.3-based Peripheral Device Drivers
· DSP Chip Support Library (CSL)
· TMS320C6474 Evaluation Module (EVM)

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~ DSP News

DSP News

TMS320C6474
ξ for designers that must integrate multiple digital signal processors (DSPs) on a board
ξ in order to handle performance-hungry tasks, such as
ξ simultaneously processing on multiple channels or executing multiple software applications concurrently
ξ can now realize significant cost, power and board space savings
ξ with a new high performance multicore DSP from Texas Instruments Incorporated (TI) (NYSE: TXN)

The TMS320C6474
ξ integrates three of TI's industry-leading TMS320C64x+(TM) cores
ξ running at 1 GHz each on a single die,
ξ delivering 3 GHz of raw DSP performance that
ξ consumes 1/3 less power
ξ at 2/3 less DSP cost over discrete processing solutions
ξ provides significant system integration for customers currently utilizing DSP farms for
ξ communications infrastructure, medical imaging, military communications and
ξ industrial vision inspection end equipments and markets

Feedback
ξ TI is putting old wine in new bottle; specifications seems similar to C6488 3 Core DSP which was launched more than a year ago

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