California's (CA) Hardware Sensing Δ 15th of September 2014 Ω 3:52 AM

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~ U.S. Department of Energy’s Lawrence Berkeley National Laboratory ~ Tensilica ~ AMD	~ Intel ~ Kateeva ~ sense for Ξ	~ sense for Ξ ~ sense for Ξ ~ sense for Ξ
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«U.S. Hardware Sensing	Θ	Θ
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~ U.S. Department of Energy’s Lawrence Berkeley National Laboratory

U.S. Department of Energy’s Lawrence Berkeley National Laboratory
ξ Three researchers from the U.S. Department of Energy’s Lawrence Berkeley National Laboratory (Berkeley Lab)
ξ have proposed an innovative way to improve global climate change predictions
ξ by using a supercomputer with low-power embedded microprocessors,
ξ an approach that would overcome limitations posed by today’s conventional supercomputers

ξ In a paper published in the May issue of the International Journal of High Performance Computing Applications,
ξ Michael Wehner and Lenny Oliker of Berkeley Lab’s Computational Research Division, and
ξ John Shalf of the National Energy Research Scientific Computing Center (NERSC)
ξ lay out the benefit of a new class of supercomputers for modeling climate conditions and understanding climate change.

ξ Using the embedded microprocessor technology used in cell phones, iPods, toaster ovens and most other modern day electronic conveniences,
ξ they propose designing a cost-effective machine for running these models and improving climate predictions

ξ In April, Berkeley Lab signed a collaboration agreement with Tensilica®, Inc.
ξ to explore such new design concepts for energy-efficient high-performance scientific computer systems
ξ The joint effort is focused on novel processor and systems architectures
ξ using large numbers of small processor cores,
ξ connected together with optimized links, and
ξ tuned to the requirements of highly-parallel applications such as climate modeling

ξ Understanding how human activity is changing global climate
ξ is one of the great scientific challenges of our time
ξ Scientists have tackled this issue by developing climate models that use the historical data of factors
ξ that shape the earth’s climate, such as rainfall, hurricanes, sea surface temperatures and carbon dioxide in the atmosphere
ξ One of the greatest challenges in creating these models, however, is to develop accurate cloud simulations

ξ Although cloud systems have been included in climate models in the past,
ξ they lack the details that could improve the accuracy of climate predictions
ξ Wehner, Oliker and Shalf set out to establish a practical estimate
ξ for building a supercomputer capable of creating climate models at 1-kilometer (km) scale
ξ A cloud system model at the 1-km scale would provide rich details that are not available from existing models

ξ To develop a 1-km cloud model,
ξ scientists would need a supercomputer
ξ that is 1,000 times more powerful than what is available today
ξ building a supercomputer powerful enough to tackle this problem is a huge challenge

ξ Historically, supercomputer makers build larger and more powerful systems by increasing the number of conventional microprocessors —
ξ usually the same kinds of microprocessors used to build personal computers
ξ Although feasible for building computers large enough to solve many scientific problems,
ξ using this approach to build a system capable of modeling clouds at a 1-km scale would cost about $1 billion
ξ The system also would require 200 megawatts of electricity to operate,
ξ enough energy to power a small city of 100,000 residents.

ξ In their paper, “Towards Ultra-High Resolution models of Climate and Weather,”
ξ the researchers present a radical alternative that would cost less to build and
ξ require less electricity to operate
ξ They conclude that a supercomputer using about 20 million embedded microprocessors
ξ would deliver the results and cost $75 million to construct
ξ This “climate computer” would consume less than 4 megawatts of power and
ξ achieve a peak performance of 200 petaflops

ξ “Without such a paradigm shift, power will ultimately limit the scale and performance of future supercomputing systems, and
ξ therefore fail to meet the demanding computational needs of important scientific challenges like the climate modeling,” Shalf said.

ξ The researchers arrive at their findings by extrapolating performance data from the Community Atmospheric Model (CAM)
ξ CAM, developed at the National Center for Atmospheric Research in Boulder, Colorado,
ξ is a series of global atmosphere models commonly used by weather and climate researchers

ξ The “climate computer” is not merely a concept
ξ Wehner, Oliker and Shalf, along with researchers from UC Berkeley,
ξ are working with scientists from Colorado State University to build a prototype system
ξ in order to run a new global atmospheric model developed at Colorado State

ξ “What we have demonstrated is that in the exascale computing regime,
ξ it makes more sense to target machine design for specific applications,”Wehner said.
ξ “It will be impractical from a cost and power perspective to build general-purpose machines like today’s supercomputers.”

ξ Under the agreement with Tensilica,
ξ the team will use Tensilica’s Xtensa LX extensible processor cores as the basic building blocks
ξ in a massively parallel system design
ξ Each processor will dissipate a few hundred milliwatts of power,
ξ yet deliver billions of floating point operations per second and
ξ be programmable using standard programming languages and tools
ξ This equates to an order-of-magnitude improvement in floating point operations per watt,
ξ compared to conventional desktop and server processor chips
ξ The small size and low power of these processors allows tight integration at the chip, board and rack level
ξ and scaling to millions of processors within a power budget of a few megawatts

ξ Berkeley Lab is a U.S. Department of Energy national laboratory located in Berkeley, California.
ξ It conducts unclassified scientific research and is managed by the University of California

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~ Tensilica

»Tensilica

Overview
ξ a privately held company incorporated in July 1997
ξ is known as the leader and major innovator in configurable processor technology,
ξ with multiple patents on its easy-to-use automated processor design systems
ξ that let designers quickly and accurately modify the processor and
ξ it's companion software development and system modeling tools with exactly the configuration options and application-specific instructions needed
ξ Tensilica’s processors are the engines in system-on-chip (SOC) designs
ξ Tensilica solutions allow designers to create lower power, higher performance hardware and software for their chip designs

Tensilica has two main product lines: the configurable Xtensa processors and the pre-configured Diamond Standard processors.

Tensilica’s unique Xtensa processors
ξ are designed for high volume, embedded applications
ξ Designers can configure and extend the processor to add memories, peripherals and special functions
ξ a complete software development environment is automatically created to match each new processor configuration
ξ Often design teams are able to replace their RTL designs with Xtensa processors,
ξ adding programmability and flexibility to their designs
ξ Tensilica also offers the XPRES Compiler,
ξ which automatically creates customized Xtensa processors from standard C/C++ algorithms

Tensilica’s Diamond Standard processors
ξ are a set of 10 off-the-shelf synthesizable cores that range from area-efficient,
ξ low-power controllers to audio and video processors and a high-performance DSP,
ξ all of which lead the industry in their respective categories both in lowest power and highest performance
ξ The Diamond Standard processors are supported by an optimized set of Diamond Standard software tools and
ξ a wide range of industry infrastructure partners
ξ They are available directly from Tensilica and through a growing list of ASIC and foundry partners

Technology

A Modern, Efficient Architecture
ξ All of Tensilica’s processors are based on the proven Xtensa architecture,
ξ which is used across a wide range of electronic products,
ξ from low-cost portable consumer applications
ξ to carrier-class networking routers
ξ Whether used as an efficient programmable controller or as an audio processor, high-performance DSP or high-speed processor,
ξ the Xtensa Instruction Set Architecture (ISA) is the ideal architecture for almost any application in any market.
ξ How can one architecture the "the best" for so many different markets?
ξ Because Tensilica essentially gives you the equivalent of a $15 million architectural license
ξ to modify its processors, plus patented, automated tools that assure that your modifications will be made properly.

ξ On top of that, Tensilica's tools automatically generate a complete, matching tool chain for any configuration or set of extensions.
ξ So you always have the software support you need that exactly matches your own processor.

ξ This lets you build in your own differentiation into your products.
ξ Your products will be harder for competitors to copy,
ξ since you're using your unique processor instead of an industry standard core that anyone can purchase.

ξ for a simple controller or DSP is Diamond Standard product line of Tensilica-optimized cores, built on the same foundation
ξ picked the configuration options and/or extended the processor themselves

A Superior Instruction Set Architecture
ξ The Xtensa Instruction Set Architecture (ISA)
ξ is a 32-bit RISC architecture
ξ featuring a compact instruction set optimized for embedded designs
ξ The architecture has:
ξ a 32-bit ALU;
ξ 16, 32 or 64 general-purpose physical registers;
ξ six special purpose registers; and
ξ 80 base instructions

ξ The Xtensa ISA employs 24-bit instructions with 16-bit narrow encodings for the most common instructions
ξ These 16-and 24-bit instruction words are freely intermixed to achieve higher code density without compromising application performance.
ξ On some processors, 64-bit VLIW encoding is utilized when efficient, and
ξ these 2- or 3-issue instructions are also modelessly intermixed with 16- and 24-bit instructions
ξ The Xtensa ISA thus optimizes the size of the program instructions by minimizing both the static number of instructions
ξ (the instructions that constitute the application program) and the average number of bits per instruction

ξ The use of 24- and 16-bit instruction words, the use of compound instructions,
ξ the richness of the comparison and bit-testing instructions,
ξ zero-overhead-loop instructions,
ξ register windowing, and
ξ the use of encoded immediate values
ξ all contribute to the Diamond processors’ small code size.
ξ Thus, the 24-/16-bit Diamond processor ISA enables designers to achieve 25% to 50% lower code size compared to conventional 32-/16-bit ISA-based RISC cores
ξ Reducing code size results in smaller memory sizes and lower power dissipation
ξ – key parameters in cost-sensitive, highly integrated SOC designs.

»Xtensa 7 Configurable Processor Core

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~ AMD

AMD Developers
ξ Username: dragonxi4amd Password: amd4dragonxi Remember: Tyyne

»Athlon 64 X2
ξ a dual-core desktop CPU consisting of two Athlon 64 cores joined together on one die with additional control logic
ξ cores share one dual-channel memory controller
ξ are based on the E-stepping model of Athlon 64 and, depending on the model, have either 512 or 1024 KiB of L2 Cache per core
ξ Athlon64 X2 is capable of decoding SSE3 instructions except those few specific to Intel's architecture

Thread-level parallelism
ξ the main benefit of dual-core processors like the X2 is their ability to process more software threads at the same time
ξ by placing two cores on the same die, the X2 effectively doubles the TLP over a single-core Athlon 64 of the same speed
ξ programs often written with multiple threads and capable of utilizing dual-cores include many music and video encoding applications,
ξ and especially professional rendering programs
ξ high TLP applications currently correspond to server/workstation situations more than the typical desktop
ξ these applications can realize almost twice the performance of a single-core Athlon 64 of the same specifications
ξ multi-tasking also runs a sizable number of threads;
ξ intense multi-tasking scenarios have actually shown improvements of considerably more than two times
ξ this is primarily due to the excessive overhead caused by constantly switching threads,
ξ and could potentially be improved by adjustments to operating system scheduling code

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~ Intel

»Intel

»Next-Generation Intel® Microarchitecture

Dynamic scalability,
ξ managed cores, threads, cache, interfaces, and
ξ power for energy-efficient performance on demand.

Design and performance scalability
ξ for server, workstation, PC, and mobile demands
ξ with support for 2-8+ cores and
ξ up to 16+ threads with simultaneous multi-threading (SMT), and
ξ scalable cache sizes,
ξ system interconnects, and
ξ integrated memory controllers.

Simultaneous multi-threading
ξ brings high-performance applications into mainstream computing with
ξ 1-16+ threads optimized for a new generation multi-core processor architecture.

Scalable shared memory of Intel QuickPath technology
ξ features memory distributed to each processor
ξ with integrated memory controllers and
ξ high-speed point-to-point interconnects
ξ to unleash the performance of next-generation Intel® multi-core processors.

Multi-level shared cache
ξ improves performance and efficiency
ξ by reducing latency to frequently used data.

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~ Kateeva

»Kateeva
aims to reduce the cost of making flexible and large-scale OLEDs
pioneered a new inkjet printing manufacturing equipment solution
that will enable such OLEDs to be produced over large areas and in high volume – with longer lifetimes, higher yields and lower costs
solves key manufacturing challenges that previously prevented the well-proven inkjet technique from scaling to perform reliable, high-volume OLED printing
for OLED producers of curved, bendable, and flexible displays, as well as large displays like 55” TVs, it’s a breakthrough
It represents the industry’s first economically viable and production-worthy technique to use printing for low-cost mass-production of OLED displays
founded in 2008 and headquartered in Silicon Valley the team is staffed by OLED, ink and printing experts,
as well as experienced semiconductor and FPD equipment executives
intends to put “Dream Displays”, with their incredible clarity, performance and low-power advantages, within affordable reach

OLED displays
are now a practical reality
prized for its performance and low-power advantages,
OLED is already the preferred display technology for smart phones, digital cameras and other mobile devices
by one estimate, mobile phone displays accounted for 71% of the US$4.9 billion 2012 OLED market
within five years, it’s expected that more than half of all new phone displays will be OLED-based

The next natural leap for OLEDs is flexible and large-scale displays.
55” OLED TVs debuted in the summer of 2013, fulfilling the promise of a spectacular viewing experience
—grander by far than LCDs—but with a steep price tag.
Cost notwithstanding, reviewers raved about truer-than-life color and
ultra-realistic image quality—made possible in part by the high contrast ratios enabled by OLED technology

Flexible OLED displays
unlike rigid OLED screens which are built on glass substrates,
flexible OLED technology uses plastic substrates which enables companies to manufacture paper-thin,
ultra-light products in a variety of shapes to suit the application purpose,
think wearable consumer electronics like smart watches.

The engine of future OLED Display Innovation is inkjet printing—a proven technology,
long established in graphics arts and now-re-imagined as a manufacturing solution for OLED mass production.
When optimized with novel hardware and process techniques, and
leveraging new ink innovations by OLED materials companies,
inkjet printing enables flexible and large-scale OLEDs to be manufactured over broad areas and
in high volume—with higher yields and lower production costs.

Investors
»Samsung Venture Invest

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